Cranium Network Interface: Architecture and Implementation

As the performance of networks and processors increases, the performance of the network interface becomes an increasingly significant bottleneck in the overall performance of the parallel or distributed system. The bottleneck persists because it is fundamentally difficult to design and construct network interfaces. We seek to reduce the difficulty by developing a generic network interface template architecture called Cranium. Key aspects of this architecture are hardware support for argument checking, data movement (DMA) and efficient handlers for both short messages and large messages. Cranium provides protected direct access to user-level programs. Cranium is also compatible with networks that may deliver packets out-of-order; there is zero penalty for unordered packets. We introduce the Cranium architecture and describe a related implementation project called ChaosLAN. This work may not be copied or reproduced in whole or in part for any commercial purpose. Permission to copy in whole or in part without payment of fee is granted for nonprofit educational and research purposes provided that all such whole or partial copies include the following: a notice that such copying is by permission of Mitsubishi Electric Information Technology Center America; an acknowledgment of the authors and individual contributions to the work; and all applicable portions of the copyright notice. Copying, reproduction, or republishing for any other purpose shall require a license with payment of fee to Mitsubishi Electric Information Technology Center America. All rights reserved. Copyright c Mitsubishi Electric Information Technology Center America, 1998 201 Broadway, Cambridge, Massachusetts 02139 1. First printing, October 26, 1998